1. Field of the Invention
The present invention relates to a display device for displaying images, and, more particularly, to a display device for driving pixel elements provided in correspondence to pixels by using a holding voltage of a capacitor.
2. Description of the Background Art
Conventionally, liquid crystal displays (LCD) have been known as one type of display devices. In LCDs, liquid crystal displays with a thin-film transistor driving system (TFT-LCD) utilizing thin film transistors (TFTs) have been known, in which a transistor (TFT) on an amorphous silicon (a-Si) semiconductor thin film or a polycrystalline silicon (p-Si) semiconductor thin film is used as a base material (an active layer), and a channel and a source/drain are formed on the active layer. In particular, an active matrix type liquid crystal panel, in which a TFT serving as a switch of video signals corresponding to a display element, has superior picture quality such as contrast and response speed characteristics, since the driving voltage for the display pixel element is held by the switching operation of the TFT. Thus, such active matrix type LCD has been widely used as a monitor of a mobile-type personal computer and a desk top personal computer or a projection-type monitor a for displaying still images and motion picture images.
FIG. 44 is a diagram schematically showing a construction of a conventional color liquid crystal display. In FIG. 44, the conventional color liquid crystal display includes: a liquid crystal display section 1002 in which unit display elements 1001, each containing pixels of three colors of red (R), green (G) and blue (B), are arranged in a matrix of rows and columns; a vertical scanning circuit 1003 for successively selecting scanning lines 1010 of this liquid crystal display section 1002; and a horizontal scanning circuit 1006 for transmitting video signals to the respective columns of the liquid crystal display section 1002.
In liquid crystal display section 1002, scanning lines 1010 are provided corresponding to the respective rows of unit display elements of liquid crystal display section 1002, and by selecting one scanning line, unit display elements 1001 of one row are simultaneously selected.
In this liquid crystal display section 1002, data lines 1011 are provided corresponding to the respective rows of unit display elements 1001. These data lines 1011 are arranged corresponding to the respective rows of pixels of three colors of R, G and B.
Vertical scanning circuit 1003 includes a shift register circuit 1004 for generating a signal for successively selecting scanning lines 1010 of liquid crystal display section 1002, and a buffer circuit 1005 for buffering an output signal from shift register circuit 1004 and driving scanning lines 1010 to a selected state. A vertical synchronizing signal and a horizontal synchronizing signal are applied to a shift register circuit 1004 from a display control circuit, and scanning lines 1010 are successively scanned in the vertical direction in accordance with this horizontal synchronizing signal. Upon receipt of a vertical synchronizing signal, the driving sequence returns to the leading scanning line and the scanning lines are again successively driven. With respect to the sequence in which vertical scanning circuit 1003 drives scanning lines 1010, there are an interlace system for successively driving alternate scanning lines to a selected state and a non-interlace system for successively driving scanning lines 1010 to the selected state.
Horizontal scanning circuit 1006 includes: shift register circuit 1007 for frequency-dividing the horizontal synchronizing signal to generate signals for successively selecting the data lines of liquid crystal display section 1002 through a shifting operation; a buffer circuit 1008 for buffering the output signal of shift register circuit 1007; and a switching circuit 1009, rendered conductive in accordance with a selection signal from buffer circuit 1008, for transmitting a video signal (data signal) received from an image processing unit through common image data lines 1013 to corresponding data lines 1011. Data signals corresponding to respective pixels R, G and B are applied to this common image data lines 1013 in parallel with each other.
A switching circuit 1009 also includes switching elements SW provided corresponding to respective pixels of three colors R, G and B, and transmits data signals to data lines 1011 provided corresponding to the pixels of three colors R, G and B on the corresponding columns in parallel with each other, in accordance with a selection signal outputted from buffer circuit 1008. Thus, in unit display element 1001, data corresponding to pixels of three colors of R, G and B are simultaneously written, and the liquid crystal in the corresponding position is driven in accordance with these written data.
This display element 1001 includes a capacitor for maintaining a voltage for driving the liquid crystal display and this capacitor is coupled to common electrode line 1012. This common electrode line 1012 is arranged in common to unit display elements 1001 contained in liquid crystal display section 1002.
FIG. 45 is a diagram schematically showing a construction of a pixel element corresponding to a unit color pixel of one color in unit display element 1001 shown in FIG. 44. In FIG. 45, a unit color pixel element contained in unit display element 1001 includes: a liquid crystal element 1102; a sampling TFT 1001, rendered conductive in response to a signal on scanning line 1010, for coupling liquid crystal element 1102 to data line 1011; and a voltage holding capacitance element 1103 for holding a voltage supplied to a voltage holding node 1106 through sampling TFT 1001. This voltage holding capacitance element 1103 is connected between common electrode line 1012 and voltage holding node 1106.
Liquid crystal element 1102 is connected between voltage holding node 1106 and a counter electrode 1105, and has its transmittance varied in accordance with the voltage between counter electrode 1105 and voltage holding node 1106. Thus, the luminance of a color filter arranged to this liquid crystal element 1102 is adjusted. A parasitic capacitance 1104 exists to this liquid crystal element 1102. Now, a description will be briefly given of the operation of unit color pixel elements shown in FIG. 45.
When sampling TFT 1101 is set to an on-state by a signal on scanning line 1010, a data signal, applied to signal line 1011 through common image data line 1013 shown in FIG. 44, is transmitted to voltage holding node 1106 through this sampling TFT 1101. In accordance with a voltage transmitted to this voltage holding node 1106, charges are accumulated in voltage holding capacitance element 1103 and parasitic capacitance 1104.
In the case of the so-called line sequential driving system, unit pixels 1001 of one row, connected to this scanning line 1010, are successively selected in accordance with an output signal of horizontal scanning circuit 1006 shown in FIG. 44, so that data signals are written into the respective selected unit pixels. Upon completion of writing of data signals to unit pixels in one scanning line 1010, vertical scanning circuit 1003, shown in FIG. 44, drives scanning line 1010 on the next row to the selected state, and a data signal writing is carried out on unit pixels on the next row.
The voltage of scanning line 1010 in the non-selected state is set to the ground voltage level or a negative voltage level so that sampling TFT 1101 connected to scanning line 1010 in the non-selected state is maintained in the off-state. Therefore, a voltage written in this voltage holding node 1106 is maintained by voltage holding capacitance element 1103 and parasitic capacitance 1104 until the next scanning by vertical scanning circuit 1003.
After vertical scanning circuit 1003 scans all rows (referred to as 1 frame) in this liquid crystal display section 1002, a positive voltage is again applied to this scanning line 1010, and sampling TFT 1101 turns conductive, so that a voltage is written in liquid crystal element 1102 and voltage holding capacitance element 1103 from the corresponding data signal line 1011 through sampling TFT 1101. Therefore, each unit display element has a holding voltage written successively at every frame.
Since liquid crystal element 1102 degrades in characteristics when a dc (direct current) voltage is applied thereto, an ac (altering current) driving is carried out on liquid crystal element 1102. In other words, writing and voltage holding of each unit color pixel are carried out by writing a voltage of a positive polarity and a voltage of a negative polarity relative to a voltage in counter electrode 1105 in data signal line 1011 at every frame alternately.
Generally, this frame frequency is set to 60 Hertz, and a voltage of an inverted polarity of a positive and a negative polarity is applied to voltage holding node 1106 alternately, so that the liquid crystal driving frequency is set to ½ times the frame frequency, and normally set to 30 Hertz.
The voltage difference between the voltage written and held in voltage holding node 1106 and the voltage of the counter electrode 1105 is averaged over time, and a voltage Vrms effectively applied to liquid crystal element 1102 is determined. In accordance with the effective voltage Vrms, the orienting state of liquid crystal element 1102 is determined so that the light transmittance of the liquid crystal element is controlled and the display state is determined.
In the case of a liquid crystal driving frequency of 30 Hertz, noise referred to as flicker appears on the display screen, resulting in degradation in displayed image quality. In order to reduce such flicker, conventionally, a system for suppressing flicker by alternately inverting the polarity of a liquid crystal driving voltage for pixels adjacent to each other longitudinally as well as laterally has been used.
In this liquid crystal display device, when a data signal is written in one unit display element, this written voltage needs to be maintained by liquid crystal display element 1102 and holding capacitance element 1103 until the next writing is again carried out, that is, for one frame period. The voltage of this voltage holding node 1106 tends to lower due to the finite resistivity of liquid display element 1102 and leakage current in sampling TFT 1101 and elsewhere.
As illustrated in FIG. 46, in the case of an operation with a normal frame period of 60 Hertz (Hz), since each unit pixel element has the holing voltage rewritten every frame period PF (= 1/60 second), there is only a slight drop in voltage of the pixel node (voltage holding node), resulting in a small variation in the reflectance (luminance) in the pixel liquid crystal element. Therefore, it is possible to sufficiently suppress degradation in the display quality such as flicker and reduction in contrast. Here, in FIG. 46, the axis abscissa represents time and the ordinate represents reflectance (luminance) of the unit color pixel element.
In the liquid crystal display device, most of currents are consumed for charging and discharging a capacitance at a crossing of the scanning line and data signal line and the capacitance of a liquid crystal element between the interconnection line (scanning lines and data signal lines) and the counter electrode formed on the entire surface of the opposing substrate, every time of selecting sampling TFT 1101. Vertical scanning circuit 1003 is operated with frequency of the frame frequency multiplied by the number of scanning signal lines, and horizontal scanning circuit 1006 is operated with the frequency of the frame frequency times the number of scanning signal line times the number of data signal lines. Therefore, the capacitance between the interconnection lines and the capacitance between the interconnection lines and the counter electrodes are charged and discharged at the operation frequencies of these vertical scanning circuit 1003 and horizontal scanning circuit 1006, with the result that the power consumption becomes greater.
In order to reduce this power consumption, it is considered to be advantageously effective to reduce the operation frequencies of these vertical scanning circuit 1003 and the horizontal scanning circuit 1006 or to intermittently operate these scanning circuits 1003 and 1006.
As illustrated in FIG. 47, when the operation frequencies of horizontal and vertical scanning circuits 1003 and 1006 are so decreased as to carry out a writing on each unit color pixel at a frequency Pfr, pixel node (voltage holding node) 1106 causes an extremely great voltage drop, causing a great variation in reflectance (luminance). Here, in FIG. 47 also, the abscissa represents time and the ordinate represents reflectance (luminance) of the unit color pixel element. The reflectance is in proportion to the stored voltage in the pixel node. When a display is made based upon the writing at such a low speed (low frequency), the voltage in pixel node 1106 varies greatly to greatly vary the reflectance (luminance), and such voltage drop is observed as flicker on the display screen, causing degradation in display image quality. Moreover, the average voltage to be applied to this liquid crystal element is lowered, failing to provide good contrast as well as causing a decrease in display response speed due to the low speed rewriting. Thus, problems relating to display quality arise.
Japanese Patent Laying-Open No. 9-258168(1997) proposed a method for reducing the problem of degradation in display quality due to a reduction in the operation frequency.
FIG. 48 is a diagram schematically showing a construction of one pixel in a conventional liquid crystal display unit. In FIG. 48, a display pixel includes: a sampling TFT 1131 selectively rendered conductive in accordance with a signal Gm on scanning line 1010 and transmitting a data signal Di on data signal line 1011 to an internal node 1133 when made conductive; a voltage holding capacitance element 1132 connected between internal node 1133 and common electrode line 1121; a pixel driving TFT 1134 selectively made conductive in response to the voltage of internal node 1133 to electrically connect a common electrode line 1121 and a transparent electrode 1135 when made conductive; and a counter electrode 1136 for receiving a driving voltage Vcnt from counter electrode driving circuit 1122.
Display elements, shown in FIG. 48, are arranged in row and column directions in a matrix of rows and columns. Common electrode line 1121, which is commonly connected to all the display pixels contained in this display section, receives a common electrode voltage Vcom from a common electrode driving circuit 1120.
A counter electrode 1136 is formed on the entire face on an opposing substrate commonly to display pixels formed in a display element panel section. Polarizing plates are provided on the outsides of both transparent electrode 1135 and the counter substrate, and a back light is provided on one of these sides. The display pixels shown in FIG. 48 are a single color display pixels, and the display pixels shown in FIG. 48 are arranged corresponding to the respective three colors of R, G and B.
Referring to a signal waveform diagram shown in FIG. 49, a description will be given of the operation sequence of display pixels shown in FIG. 48. With respect to a scanning line selected by the scanning line selection circuit, when a voltage that is not less than a threshold voltage of sampling TFT 1131 is transmitted on scanning line 1010, this scanning line 1010 is selected and a row of pixels connected to this scanning line 1010 are simultaneously selected. In the point sequential system, a data signal Di is successively transmitted onto data signal line 1011 from a data writing circuit, while in the line sequential system, respective data signals are transmitted to display pixels connected to this scanning line 1010 simultaneously.
When a data signal Di on data signal line 1011 charges voltage holding capacitance element 1132 through sampling TFT 1131, voltage Vmem of internal node 1133 changes in response to written data signal Di. FIG. 49 shows a case in which a writing data voltage of a logical high (H) level is first transmitted at the time of sampling. When the voltage level of internal node 1133 goes to the logical H level, the corresponding pixel driving TFT 1134 turns conductive to connect transparent electrode 1135 to common electrode line 1121, and accordingly, the voltage Vdp of this transparent electrode 1135 is made equal to the voltage Vcom on common electrode line 1121.
The counter electrode voltage Vcnt supplied from counter electrode driving circuit 1122 to counter electrode line 1136 changes in polarity every sampling period (polarities of signal voltages are inverted in adjacent rows so as to suppress the generation of flicker). In accordance with this counter electrode voltage Vcnt, the voltage Vlcd between transparent electrode 1135 and counter electrode 1136 is changed in accordance with this counter electrode voltage Vcnt so that the orienting state of liquid crystal is changed to turn on-state.
When the sampling voltage Vmem is at a logical low (L) level, pixel driving TFT 1134 is in a non-conductive state so that transparent electrode 1135 serving as a display electrode and common electrode line 1121 are disconnected from each other. Thus, since the voltage (Liquid crystal driving voltage Vcnt) on this counter electrode 1136 is not applied to the liquid crystal, so that the voltage between electrodes in liquid crystal is at L level, and the liquid crystal maintains the non-conductive state.
Therefore, in the construction of the display pixels shown in FIG. 48, data signal Di applied to the voltage holding capacitance element is utilized as a signal voltage for controlling the display state. The charges, once accumulated in the voltage holding capacitance element 1132, gradually decrease in amount due to leak currents of sampling TFT 1131 and sampling capacitor (voltage holding capacitance element) 1132 during a period (one frame period) until the corresponding scanning line 1010 will be next selected. However, until the voltage of internal node 1133 has dropped below a threshold voltage of pixel driving TFT 1134, pixel driving TFT 1134 maintains the conductive state so that transparent electrode 1135 and common electrode 1121 are electrically connected, resulting in no change in the display state.
In accordance with the construction shown in FIG. 48, scanning line 1010 and data signal line 1011 need to be driven only when the display contents are rewritten. When the display state is not required to change, the display state is maintained by only applying the liquid crystal driving voltage (Vcnt) between common electrode line 1121 and counter electrode 1136. Thus, it is possible to eliminate the necessity of driving scanning lines and data signal lines in maintaining the display contents, and consequently to possibly reduce the power consumption.
In the construction of the display pixels shown in FIG. 48, the data signal (sampling voltage) Vmem gradually decreases due to insulator leak currents in pixel driving TFT 1134 and voltage holding capacitance element 1132, and an off-leak current of sampling TFT 1131. When this voltage level of internal node 1133 lowers to cause pixel driving TFT 1134 to turn off-state, the display state is changed. Therefore, when no change is made in the display state, it is necessary to restore (refresh) the sampling voltage periodically.
FIG. 50 shows an example of a construction of a conventional display system. In FIG. 50, this display system includes: a processor (CPU) 1200 for controlling the display of images, an external memory 1202 for storing image data from an image signal processing unit, not shown, and for successively outputting image data therefrom under control of processor 1200; and a display device 1204 for displaying images in accordance with the image data from external memory 1202.
Display device 1204 has a display panel constituted by display pixels shown in FIG. 48. External memory 1202 is constituted by, for example, a static random access memory (SRAM) or a video memory, and stores image data for this display device 1204. When the display state of display device 1204 is not changed, image data used for refreshing is stored in this external memory 1202. Therefore, when the sampling voltage (holding voltage) Vmem of each display pixel is refreshed in display device 1204, it is necessary to read image data stored in external memory 1202 and to supply the read out refreshing data to display device 1204. When external memory 1202 is constituted by an SRAM, the cost of the external memory is comparatively high. Since a pixel data signal is transmitted between external memory 1202 and display device 1204 upon refreshing, power is consumed in the wiring between external memory 1202 and display device 1204 and in external memory 1202, resulting in a problem of increased power consumption for refreshing.